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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_tdm_config_rx_t Struct Reference<div class="ingroups"><a class="el" href="group__group__tdm.html">TDM/I2S      (Time Division Multiplexing/Inter-IC Sound)</a> &raquo; <a class="el" href="group__group__tdm__data__structures.html">Data Structures</a></div></div>  </div>
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<div class="textblock"><p><a class="el" href="structcy__stc__tdm__config__rx__t.html" title="cy_stc_tdm_config_rx_t ">cy_stc_tdm_config_rx_t</a> </p>
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Data Fields</h2></td></tr>
<tr class="memitem:a4a4839e77c81bf1fe7c32b8edf67befe"><td class="memItemLeft" align="right" valign="top"><a id="a4a4839e77c81bf1fe7c32b8edf67befe"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a4a4839e77c81bf1fe7c32b8edf67befe">enable</a></td></tr>
<tr class="memdesc:a4a4839e77c81bf1fe7c32b8edf67befe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables/Disables TDM RX. <br /></td></tr>
<tr class="separator:a4a4839e77c81bf1fe7c32b8edf67befe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63c8002ff22b728f1323736fcc9bffcd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a63c8002ff22b728f1323736fcc9bffcd">masterMode</a></td></tr>
<tr class="memdesc:a63c8002ff22b728f1323736fcc9bffcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master mode/Slave mode configuration.  <a href="#a63c8002ff22b728f1323736fcc9bffcd">More...</a><br /></td></tr>
<tr class="separator:a63c8002ff22b728f1323736fcc9bffcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0727e5bcc4e0161c8128b90e9b208248"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga3e7c9522bd7a7e179487ac26fcec0129">cy_en_tdm_ws_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a0727e5bcc4e0161c8128b90e9b208248">wordSize</a></td></tr>
<tr class="memdesc:a0727e5bcc4e0161c8128b90e9b208248"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX word length.  <a href="#a0727e5bcc4e0161c8128b90e9b208248">More...</a><br /></td></tr>
<tr class="separator:a0727e5bcc4e0161c8128b90e9b208248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a773f6c3e94da293783cc403f5fa03b13"><td class="memItemLeft" align="right" valign="top"><a id="a773f6c3e94da293783cc403f5fa03b13"></a>
<a class="el" href="group__group__tdm__enums.html#gab0793a864efd973075babaea02b09fe2">cy_en_tdm_word_extend_cfg_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a773f6c3e94da293783cc403f5fa03b13">signExtend</a></td></tr>
<tr class="memdesc:a773f6c3e94da293783cc403f5fa03b13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word extension <a class="el" href="group__group__tdm__enums.html#gab0793a864efd973075babaea02b09fe2">cy_en_tdm_word_extend_cfg_t</a>. <br /></td></tr>
<tr class="separator:a773f6c3e94da293783cc403f5fa03b13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e22307c8826f9e40922dd4397ec712f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a9e22307c8826f9e40922dd4397ec712f">format</a></td></tr>
<tr class="memdesc:a9e22307c8826f9e40922dd4397ec712f"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX data format, <a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>.  <a href="#a9e22307c8826f9e40922dd4397ec712f">More...</a><br /></td></tr>
<tr class="separator:a9e22307c8826f9e40922dd4397ec712f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f68fc2bd9634c1abefa70fcc42d2dd4"><td class="memItemLeft" align="right" valign="top">uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a0f68fc2bd9634c1abefa70fcc42d2dd4">clkDiv</a></td></tr>
<tr class="memdesc:a0f68fc2bd9634c1abefa70fcc42d2dd4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock.  <a href="#a0f68fc2bd9634c1abefa70fcc42d2dd4">More...</a><br /></td></tr>
<tr class="separator:a0f68fc2bd9634c1abefa70fcc42d2dd4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8dc6198e67afeaf16a2119b88d8d5a52"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a8dc6198e67afeaf16a2119b88d8d5a52">clkSel</a></td></tr>
<tr class="memdesc:a8dc6198e67afeaf16a2119b88d8d5a52"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface clock "clk_if" selection, <a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>.  <a href="#a8dc6198e67afeaf16a2119b88d8d5a52">More...</a><br /></td></tr>
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<a class="el" href="group__group__tdm__enums.html#ga740465810e855730300bda1ca68a3f29">cy_en_tdm_sckpolarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a91573eeee10cab242b7211c94b5e4981">sckPolarity</a></td></tr>
<tr class="memdesc:a91573eeee10cab242b7211c94b5e4981"><td class="mdescLeft">&#160;</td><td class="mdescRight">RX clock polarity, 0: as is and 1: inverted <a class="el" href="group__group__tdm__enums.html#ga740465810e855730300bda1ca68a3f29">cy_en_tdm_sckpolarity_t</a>. <br /></td></tr>
<tr class="separator:a91573eeee10cab242b7211c94b5e4981"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add840dbffbe15eaf6b2c53e7e57e3610"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__tdm__enums.html#gae049ad85366a084a1bbf3ef69109c0c5">cy_en_tdm_fsyncpolarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#add840dbffbe15eaf6b2c53e7e57e3610">fsyncPolarity</a></td></tr>
<tr class="memdesc:add840dbffbe15eaf6b2c53e7e57e3610"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel synchronization polarity:'false':used "as is".  <a href="#add840dbffbe15eaf6b2c53e7e57e3610">More...</a><br /></td></tr>
<tr class="separator:add840dbffbe15eaf6b2c53e7e57e3610"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada33c42d9387cc8098fc43ad1aa881f8"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#ada33c42d9387cc8098fc43ad1aa881f8">lateSample</a></td></tr>
<tr class="memdesc:ada33c42d9387cc8098fc43ad1aa881f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface late sample delay.  <a href="#ada33c42d9387cc8098fc43ad1aa881f8">More...</a><br /></td></tr>
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<a class="el" href="group__group__tdm__enums.html#ga0beaff668ba6388ecccaf62524a37449">cy_en_tdm_fsyncformat_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a09c56a3ee7782b5ffcdd29b82dfb75ab">fsyncFormat</a></td></tr>
<tr class="memdesc:a09c56a3ee7782b5ffcdd29b82dfb75ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel synchronization pulse format <a class="el" href="group__group__tdm__enums.html#ga0beaff668ba6388ecccaf62524a37449">cy_en_tdm_fsyncformat_t</a>. <br /></td></tr>
<tr class="separator:a09c56a3ee7782b5ffcdd29b82dfb75ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e1c36506959270e50e2cc946a12105d"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a5e1c36506959270e50e2cc946a12105d">channelNum</a></td></tr>
<tr class="memdesc:a5e1c36506959270e50e2cc946a12105d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Number of channels in the frame: 1 to 32 channels supported.  <a href="#a5e1c36506959270e50e2cc946a12105d">More...</a><br /></td></tr>
<tr class="separator:a5e1c36506959270e50e2cc946a12105d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5ff9a86f57a96894f42fd0745b75269"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#af5ff9a86f57a96894f42fd0745b75269">channelSize</a></td></tr>
<tr class="memdesc:af5ff9a86f57a96894f42fd0745b75269"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel Size.  <a href="#af5ff9a86f57a96894f42fd0745b75269">More...</a><br /></td></tr>
<tr class="separator:af5ff9a86f57a96894f42fd0745b75269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaaf9b8f58e9db1688b998589cf57dc30"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#aaaf9b8f58e9db1688b998589cf57dc30">chEn</a></td></tr>
<tr class="memdesc:aaaf9b8f58e9db1688b998589cf57dc30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channels enabled: channel i is controlled by bit chEn[i].  <a href="#aaaf9b8f58e9db1688b998589cf57dc30">More...</a><br /></td></tr>
<tr class="separator:aaaf9b8f58e9db1688b998589cf57dc30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a131501de1e9ecad473879167462d09e7"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a131501de1e9ecad473879167462d09e7">fifoTriggerLevel</a></td></tr>
<tr class="memdesc:a131501de1e9ecad473879167462d09e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger level.  <a href="#a131501de1e9ecad473879167462d09e7">More...</a><br /></td></tr>
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<tr class="memitem:a1c21b39d6dfa8bcf2a1bb167b5fc19a7"><td class="memItemLeft" align="right" valign="top"><a id="a1c21b39d6dfa8bcf2a1bb167b5fc19a7"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#a1c21b39d6dfa8bcf2a1bb167b5fc19a7">signalInput</a></td></tr>
<tr class="memdesc:a1c21b39d6dfa8bcf2a1bb167b5fc19a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controls routing to the RX slave signaling inputs (FSYNC/SCK): '0': RX slave signaling independent from TX signaling : '1': RX slave signaling inputs driven by TX Slave: '2': RX slave signaling inputs driven by TX Master: <br /></td></tr>
<tr class="separator:a1c21b39d6dfa8bcf2a1bb167b5fc19a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4291885f456934f8bca75a44dca75d6"><td class="memItemLeft" align="right" valign="top"><a id="aa4291885f456934f8bca75a44dca75d6"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tdm__config__rx__t.html#aa4291885f456934f8bca75a44dca75d6">i2sMode</a></td></tr>
<tr class="memdesc:aa4291885f456934f8bca75a44dca75d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IF set to 1 the IP is configured for I2S mode else for TDM mode. <br /></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="a63c8002ff22b728f1323736fcc9bffcd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a63c8002ff22b728f1323736fcc9bffcd">&#9670;&nbsp;</a></span>masterMode</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a> cy_stc_tdm_config_rx_t::masterMode</td>
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<p>Master mode/Slave mode configuration. </p>
<p><a class="el" href="group__group__tdm__enums.html#gacf788712265d4ce0fdbf0b9aed4bb38f">cy_en_tdm_device_cfg_t</a> </p>

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<a id="a0727e5bcc4e0161c8128b90e9b208248"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0727e5bcc4e0161c8128b90e9b208248">&#9670;&nbsp;</a></span>wordSize</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga3e7c9522bd7a7e179487ac26fcec0129">cy_en_tdm_ws_t</a> cy_stc_tdm_config_rx_t::wordSize</td>
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<p>RX word length. </p>
<p>Channel size must be greater or equal to the word size. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9e22307c8826f9e40922dd4397ec712f">&#9670;&nbsp;</a></span>format</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a> cy_stc_tdm_config_rx_t::format</td>
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<p>RX data format, <a class="el" href="group__group__tdm__enums.html#ga17c76544100c74ac3f72bd1a23131acf">cy_en_tdm_format_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0f68fc2bd9634c1abefa70fcc42d2dd4">&#9670;&nbsp;</a></span>clkDiv</h2>

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          <td class="memname">uint16_t cy_stc_tdm_config_rx_t::clkDiv</td>
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<p>Should be set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock. </p>
<p>Only for Master Mode </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8dc6198e67afeaf16a2119b88d8d5a52">&#9670;&nbsp;</a></span>clkSel</h2>

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          <td class="memname"><a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a> cy_stc_tdm_config_rx_t::clkSel</td>
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<p>Interface clock "clk_if" selection, <a class="el" href="group__group__tdm__enums.html#ga6e68e27138e141adeaca8402fd032e37">cy_en_tdm_clock_sel_t</a>. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#add840dbffbe15eaf6b2c53e7e57e3610">&#9670;&nbsp;</a></span>fsyncPolarity</h2>

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<p>Channel synchronization polarity:'false':used "as is". </p>
<p>'true': inverted. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ada33c42d9387cc8098fc43ad1aa881f8">&#9670;&nbsp;</a></span>lateSample</h2>

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<p>Interface late sample delay. </p>
<p>Slave configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_in
  "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_in" (half a cycle delay).
  Master configuration: "false": Sample PCM bit value on rising edge or falling edge of receiver "rx_sck_out".
  "true": Sample PCM bit value on falling edge or rising edge of receiver "rx_sck_out" (half a cycle delay). RISING = 0 FALLING = 1 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5e1c36506959270e50e2cc946a12105d">&#9670;&nbsp;</a></span>channelNum</h2>

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<p>Number of channels in the frame: 1 to 32 channels supported. </p>
<p>In I2S mode number of channels should be 2. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af5ff9a86f57a96894f42fd0745b75269">&#9670;&nbsp;</a></span>channelSize</h2>

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<p>Channel Size. </p>
<p>Channel size must be greater or equal to the word size. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aaaf9b8f58e9db1688b998589cf57dc30">&#9670;&nbsp;</a></span>chEn</h2>

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<p>Channels enabled: channel i is controlled by bit chEn[i]. </p>
<p>For example : In I2S mode for 2 channels the chEn will be 0x3 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a131501de1e9ecad473879167462d09e7">&#9670;&nbsp;</a></span>fifoTriggerLevel</h2>

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<p>Trigger level. </p>
<p>When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated. </p>

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